Modern SOCs (System-On-Chip) use high-speed clock generators in many locations across the chip, requiring a high-quality reference clock. The reference clock (REFCLK) for an SOC is generally sourced from an off-chip crystal or some other such source. It is important that the REFCLK signal is distributed across the chip with minimal jitter. For that distribution, a CML (Current Mode Logic) circuit is preferred for repeaters/buffers as it introduces less voltage-dependent jitter compared to other CMOS clock distribution solutions.
Though a CML circuit topology generally has less sensitivity to power supply fluctuations compared to a CMOS topology, it is still sensitive to voltage changes and hence it is preferred to connect the power pins of CIVIL circuits to a regulated power supply that is stable with less variation. But such a regulated supply is difficult to distribute all over the chip as needed for these clock distribution circuits. Therefore, SOC designers are often forced to connect CML circuits to other voltage supplies which have higher dynamic fluctuations and higher operating range across all conditions and workloads.
A wide variation in the supply voltage not only makes it difficult to function without errors at lower supply voltages, but more importantly degrades jitter performance of traditional CIVIL circuits like CIVIL buffers and CML receivers (CIVIL to CMOS converter).
One way these issues are addressed in the art is by restricting the placement of CML buffers to only areas where a regulated supply is available, and adjusting the clock distribution tree accordingly. The circuits which receive the clock may be moved in some cases if possible. This solution poses heavy limitations in overall floorplanning of the chip and results in a sub-optimized clock distribution network.
Another solution is to generate a stable voltage reference like BGR (Band Gap Reference) that can be used to produce a constant current that is not very sensitive to power supply fluctuations. This option is not viable for lower power supplies that are normally targeted in SOCs for battery power optimization and other power management features.
A third solution is to use a simple resistor-divider derived reference voltage. This option results in higher (above optimal) jitter in each CML buffer circuit, thereby restricting the maximum number of repeaters allowed in a distribution path, and restricting the sharing of CML lines across various corners of the chip that need reference clock.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.